What happened
High-resolution die shots of Intel's Panther Lake-H processors, part of the Core Ultra 300-series, reveal their disaggregated architecture. The compute tile, fabricated on Intel's 18A process, integrates CPU cores, an 8MB memory-side cache, and media/display engines. The graphics tile features 12 Intel Xe3 clusters and 16MB of L2 cache. The I/O tile includes a Thunderbolt 5 controller, Wi-Fi/Bluetooth, and PCIe 5.0/4.0 PHYs. This tiled approach allows for improved manufacturing yield by disabling defective sections.
Why it matters
The modular design of Panther Lake-H, with its 18A compute tile and advanced Xe3 graphics, offers chip architects and platform engineers increased flexibility in configuring CPU designs. The integrated 8MB memory-side cache reduces latency and bandwidth pressure, directly impacting system performance for demanding workloads. Furthermore, the ability to disable defective tile slices improves manufacturing yield, potentially reducing production costs and increasing chip availability for procurement teams. This follows Intel's broader strategy to offer 18A foundry services, enabling diverse product configurations from a common architecture.
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